1. Field of the Invention
The present invention pertains to an operation synthesis system for automatically creating, by transforming an operation in a program, particularly, a program described in a high-level language such as C language; a hardware description to implement the operation.
2. Description of Related Art
Japanese Patent Laid-Open Publication Ser. No. 2004-326463 describes an example of an operation synthesis system. The conventional system includes a Control Data Flow Graph (CDFG) creation module, a scheduling module, an allocation module, a data path creation module, and a controller creation module.
To convert or to pipeline a loop part of a program into a pipeline part, the operation synthesis system operates as below.
The CDFG creation module is disposed to create a control data flow graph using a description of operation in a C language program or the like including loop processing and non-loop processing. The CDFG creator identifies the loop part and the non-loop part. The loop part is controllable by a loop controller. The loop controller includes a shift-register function for a number of bits equivalent to the number of stages of the pipeline and makes it possible to execute loop processing of which the iteration of loops is not determined in the operation synthesis phase.
Description will now be given of problems of the conventional operation synthesis system.
It is difficult to create pipeline processing based on loop processing including a break statement and/or a do-while statement described in C language.
In the conventional technique, the loop including above description is converted into a loop description not including the break statement and the do-while statement to create pipeline processing for concurrent operation. However, it is required to transform also the algorithm and hence a large number of operation steps are necessary to convert the original description.
The difficulty in the conversion of the loop processing including a break statement and/or a do-while statement into pipeline processing is as follows. To conduct the parallel operation of the pipeline processing created using the loop part, there is required complex control for the loop leaving operation and for the operation in which part or the entire loop is stopped to execute another processing.
To operate at a high speed a loop description of which the iteration of the loop described in C language is determined in the compilation phase, it is difficult to create pipeline processing using the loop description for higher speed operation speed for the following reason. Complicated control is necessary to concurrently execute pipeline processing created on the basis of the loop of which the iteration of the loop is not determined in the program description, and hence the operation speed cannot be easily increased.
According to the related art of the operation synthesis field, a loop description of which the iteration of loop is not determined in the compilation phase is implemented using, for example, a shift register. Since this scheme employs a concrete hardware item, i.e., a shift register, it is difficult to apply the scheme to a parallelizing compiler.